Integrated circuits including dynamic random access memory (DRAM) devices are known in the art.
A DRAM is a device which includes a plurality of memory cells, and a plurality of row lines and column lines, wherein each memory cell is connected to both a row line and a column line. The row lines and column lines form a two-dimensional matrix having a plurality of intersections. A single memory cell is associated with each intersection between a row line and a column line. At each intersection, a row line is connected to selectively activate the corresponding memory cell. The memory cell includes a storage capacitor which is connected to the corresponding column line to allow conventional memory access operations such as reading, writing, or refreshing.
Many DRAMS are required to operate in mixed voltage systems. To accommodate such operation, the integrated circuits containing the DRAMS also include on-chip voltage regulators to regulate voltage down to a desired voltage range. Such voltage regulators are discussed in an article titled "A New On-chip Voltage Regulator for High Density CMOS DRAMs" by R. S. Mao et al, 1992 Symposium on VLSI Circuits Digest of Technical Papers, IEEE, 1992, which is incorporated herein by reference.
The voltage regulator uses the voltage supplied to the integrated circuit (V.sub.cc) as a reference. A problem with such regulator design is that when active pullup of a row line or column line occurs, for accessing of a memory cell, the supply voltage V.sub.cc drops. The drop in the supply voltage can be from several hundred millivolts to up to one volt. This causes problems with the voltage regulator which uses the supply voltage as a reference. Even though voltage regulators are designed to stabilize an output voltage against fluctuations in source or load, the reduction in the supply voltage is sufficiently drastic to cause the voltage regulator to reduce the operating voltage of the DRAM. This slows operation of the DRAM.